There can be errors in data transfers between hosts and memories. As memory link operations become faster to meet higher bandwidth requirements, the probability of data transfer errors in a link between memory devices and a host (e.g., system-on-chip (SoC), CPU) becomes greater. One reason is that the high speed link is more susceptible to clock jitter, PDN (Power Delivery Network) noise, etc.
To enhance reliability, an error protection scheme may be applied to the memory link. For example, a conventional memory subsystem may include error-correction-code (ECC) encoder and decoder on the host side and complimentary ECC encoder and decoder on the memory device side. When the host wishes to write data to the memory device, the host sends a WRITE command and provides WRITE DATA to the memory device over the link. To protect the WRITE DATA, the ECC encoder on the host side encodes the WRITE DATA prior to sending the WRITE DATA over the link. The ECC decoder on the memory device side decodes the encoded WRITE DATA, and the decoded WRITE DATA is stored in the memory cells of the memory device.
When the host wishes to read data from the memory device, the host sends a READ command to the memory device over the link. The memory device retrieves READ DATA from the memory cells and sends the retrieved READ DATA to the host over the link. To protect the READ DATA, the ECC encoder on the memory device side encodes the READ DATA prior to sending the READ DATA to the host. The ECC decoder on the host side decodes the encoded READ DATA, and the decoded READ DATA is provided to a requester such as the CPU.
Unfortunately, providing such a protection scheme usually increases performance latency due to the encoding and decoding overhead. Also, additional power is required, which may be particularly significant in mobile systems.